DSSC

DEPMOS Sensor with Signal Compression, Non-linear gain DEPFET sensor for the energy range 0.5-6 keV capable of taking > 600 frames at 4.5 MHz; this is a development project for Eu-XFEL led by the MPG’s Semiconductor Laboratory.

One ladder shown with quadrant mechanics and readout electronics; such a quadrant makes up ¼ of the full DSSC 1M Module.

The mechanical and thermal design is guided by extensive thermal simulations such as the one above showing the distribution of temperature over the sensors in one quadrant. Many of these simulations were performed by DESY’s central mechanics group.

This is a silicon detector for XFEL with ~ 40000 um^2 hexagonal pixels. Each pixel on the sensor chip incorporates a DEPFET, which integrates and amplifies the charge produced by X-rays hitting the pixel. Since the DEPFET has low noise and in this case a non-linear gain, DSSC can achieve both a high sensitivity and a large dynamic range. The readout ASIC has an ADC per pixel and uses memory pipelines to store a large number of images during the XFEL bunch train, which can then be read out in the interval between successive bunch trains. The DSSC project is led by MPI-HLL, Munich. The Photon Science Detector Group at DESY has the responsibility for the Mechanics/Thermal Workpackage of DSSC. This presents a challenge particularly because over 400 W are put out by the electronics in the in-vacuum detector head (by the sensors themselves, the ASICs, and the associated electronics boards). This heat must be removed within tight space constraints imposed by the need for minimal dead areas in the detection plane, i.e. tight butting of the individual 128 x 512 pixel “ladders” making up the full 1M pixel detection plane. Similarly, a desire for well-defined pixel positions drives a careful mechanical design with minimal tolerances. This is made more difficult by the desire to implement movable detector quadrants to optimize XFEL science output.

Project Leader: Cornelia Wunderer